Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures.

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints / Gilabert F.; Ludovici D.; Medardoni S.; Bertozzi D.; Benini L.; Gaydadjiev G.N.. - STAMPA. - (2009), pp. 681-687. (Intervento presentato al convegno Complex, Intelligent and Software Intensive Systems, 2009. CISIS '09.International Conference on tenutosi a Fukuoka nel 16-19 March 2009).

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

MEDARDONI, SIMONE;BERTOZZI, DAVIDE;BENINI, LUCA;
2009

Abstract

Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures.
2009
Complex, Intelligent and Software Intensive Systems, 2009. CISIS '09
681
687
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints / Gilabert F.; Ludovici D.; Medardoni S.; Bertozzi D.; Benini L.; Gaydadjiev G.N.. - STAMPA. - (2009), pp. 681-687. (Intervento presentato al convegno Complex, Intelligent and Software Intensive Systems, 2009. CISIS '09.International Conference on tenutosi a Fukuoka nel 16-19 March 2009).
Gilabert F.; Ludovici D.; Medardoni S.; Bertozzi D.; Benini L.; Gaydadjiev G.N.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/81388
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