A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.

R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. L. Rolandi, et al. (2007). 3D Capacitive Interconnections for High Speed Interchip Communication. IEEE [10.1109/CICC.2007.4405670].

3D Capacitive Interconnections for High Speed Interchip Communication

CANEGALLO, ROBERTO;FAZZI, ALBERTO;CICCARELLI, LUCA;MAGAGNI, LUCA;NATALI, FEDERICO;GUERRIERI, ROBERTO
2007

Abstract

A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.
2007
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE
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R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. L. Rolandi, et al. (2007). 3D Capacitive Interconnections for High Speed Interchip Communication. IEEE [10.1109/CICC.2007.4405670].
R. Canegallo; A. Fazzi; L. Ciccarelli; L. Magagni; F. Natali; P. L. Rolandi; E. Jung; L. Di Cioccio; R. Guerrieri
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/70341
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