The paper describes the design of a 38 dBm monolithic power amplifier at Ku band. The amplifier has to be used as the final stage of the downlink transmitter of a TT&C system. A commercial power p-HEMT process capable of handling a power density higher than 1 W/mm of active area has been selected for the amplifier design. The power capability of this process makes it possible to integrate in a monolithic chip the functionality up today supplied by hybrid modules. Since the circuit is a space product, the attention is focused on reliability issues; therefore performances have to be matched imposing the devices to work at de-rated conditions respect to the process maximum ratings. In this perspective, the device channel temperature becomes a very tight design objective and has to be carefully controlled by means of a thermal simulator. The paper describes the three dimensional thermal model built to predict the devices thermal behavior in the environment of a finite difference thermal simulator. The design of the circuit is also described from the specifications to the final layout.
Florian C., Cignani R., Vannini G., Comparini M.C. (2005). A Ku band monolithic power amplifier for TT&C applications. LONDON : Horizon House Publications - Ltd.
A Ku band monolithic power amplifier for TT&C applications
FLORIAN, CORRADO;CIGNANI, RAFAEL;
2005
Abstract
The paper describes the design of a 38 dBm monolithic power amplifier at Ku band. The amplifier has to be used as the final stage of the downlink transmitter of a TT&C system. A commercial power p-HEMT process capable of handling a power density higher than 1 W/mm of active area has been selected for the amplifier design. The power capability of this process makes it possible to integrate in a monolithic chip the functionality up today supplied by hybrid modules. Since the circuit is a space product, the attention is focused on reliability issues; therefore performances have to be matched imposing the devices to work at de-rated conditions respect to the process maximum ratings. In this perspective, the device channel temperature becomes a very tight design objective and has to be carefully controlled by means of a thermal simulator. The paper describes the three dimensional thermal model built to predict the devices thermal behavior in the environment of a finite difference thermal simulator. The design of the circuit is also described from the specifications to the final layout.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
