Bandwidth Limits in Hall Effect-based Current Sensors

Modern power applications are demanding for small and broadband current sensors. Hall sensors are a good solution, but practical implementations are limited to a few hundred kHz. The literature offers a theoretical knowledge about the dynamic effects acting on the Hall probe but does neither define nor experimentally assess the bandwidth fundamental upper limit, since many parasitic dynamic effects perturb the inherent time response of the Hall sensor. This paper experimentally investigates the bandwidth upper limits in CMOS Hall effect-based current sensors. Based on the physics-based description of the Hall probe, the paper defines a novel, special-purpose, measurement technique, which is able to experimentally evaluate the inherent response time of the Hall probe without triggering the main parasitic effects. The paper also propose an equivalent electrical model describing the dynamic response of the Hall probe so as to better explain and understand the measurement results. Specifically, the paper identifies two bandwidth upper limits: a fundamental limit set by the intrinsic capacitance, which models the transversal charge accumulation due to the Hall effect, and a more practical limit set by the capacitive input of the electronic readout interface. Some main parasitic effects are then assess and added in the proposed model.