In this manuscript we evaluate the impact of HW power capping mechanisms on a real scientific application composed by parallel execution. By comparing HW capping mechanism against static frequency allocation schemes we show that a speed up can be achieved if the power constraint is enforced in average, during the application run, instead of on short time periods. RAPL, which enforces the power constraint on a few ms time scale, fails on sharing power budget between more demanding and less demanding application phases.
Cesarini, D., Bartolini, A., Benini, L. (2017). Benefits in Relaxing the Power Capping Constraint. New York, NY, : ACM [10.1145/3152821.3152878].
Benefits in Relaxing the Power Capping Constraint
Cesarini, Daniele;Bartolini, Andrea;Benini, Luca
2017
Abstract
In this manuscript we evaluate the impact of HW power capping mechanisms on a real scientific application composed by parallel execution. By comparing HW capping mechanism against static frequency allocation schemes we show that a speed up can be achieved if the power constraint is enforced in average, during the application run, instead of on short time periods. RAPL, which enforces the power constraint on a few ms time scale, fails on sharing power budget between more demanding and less demanding application phases.File | Dimensione | Formato | |
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