Supply voltage (V<inf>DD</inf>) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing V<inf>DD</inf> while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale V<inf>DD</inf>, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower V<inf>DD</inf> makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower V<inf>DD</inf> is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with V<inf>DD</inf>, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (V<inf>DD</inf> <0.5V). Digital PLLs (DPLLs) can operate at low V<inf>DD</inf>, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to V<inf>DD</inf> of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as V<inf>DD</inf> is varied from 0.45 to 0.7V.

A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS

BENINI, LUCA;
2015

Abstract

Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with VDD, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (VDD <0.5V). Digital PLLs (DPLLs) can operate at low VDD, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to VDD of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as VDD is varied from 0.45 to 0.7V.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
66
67
Choi, Woo-Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/545192
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