SoC Communication Architectures: Technology, Current Practice, Research, and Trends

The increasing complexity of Systems-on-Chip (SoCs) has led to the critical �design productivity gap� problem. Several strategies are being employed to cope with this problem, including an IP-based design flow, as well as platform-based designs for application domains. These approaches have critically increased the amount of on-chip communication. Since on-chip communication architectures have a significant impact on system performance, power dissipation and time-to-market, system designers, as well as the research community have focused on the issue of exploring, evaluating, and designing SoC communication architectures to meet the targeted design goals. On the other hand, aggressive scaling of VLSI technology has resulted in nanoscale effects that adversely affect interconnect performance, reliability, power dissipation, and predictability; new approaches to on-chip communication architectures (e.g., Networks-on-Chip) need to be devised in order to overcome these effects. The tutorial is structured into four parts, covering: i) scaling trends in nanometer interconnects and related methodology challenges; ii) architectural modeling and analysis of communication traffic and synthesis of current on-chip bus-based communication architectures iii) high-performance bus protocols and topologies, including design examples; and iv) emerging Network-on-Chip (NoC) paradigms for next generation designs. The tutorial begins by highlighting the key emerging issues in the domain of interconnect modeling and analysis. The implications of various nanoscale effects on VLSI interconnect performance, reliability, power dissipation and parasitic extraction are also presented. Promising new technologies including 3-D ICs and Carbon Nanotube (CNT) interconnects are outlined which have the potential to meet these interconnect challenges in the nanometer era. The second part of the tutorial will cover modeling abstractions suitable for communication centric designs, analysis technique- s for estimating bus communication traffic, and synthesis of current protocols and standards such as OCP-IP, VSIA, and AMBA. The third part of the tutorial will cover the use of advanced architectural concepts in bus-based communication architecture design, and will include design examples from the industry. Finally, the last part of the tutorial will introduce the basic concepts on Networks-on-Chip and the challenges involved in the deployment of this on-chip communication paradigm.