Clustered sleep transistor insertion is an effective leakage power reduction technique that is well-suited for integration in an automated design flow and offers a flexible tradeoff between area, delay overhead and turn-on transition time. In this work, we focus on the design of a family of sleep transistor cells, fully compatible with the physical design rules of a commercial 65nm CMOS library. We describe circuit-level and layout optimizations, as well as the cell characterization procedure required to support automated sleep transistor cell selection and instantiation in a clustered power-gating insertion flow.
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology / A. Calimera; A. Pullini; A. Visweswara Sathanur; L. Benini; A. Macii; E. Macii; M. Poncino. - STAMPA. - (2007), pp. 501-504. (Intervento presentato al convegno 17th great lakes symposium on Great lakes symposium on VLSI. Poster session 2 tenutosi a Stresa-Lago Maggiore, Italy nel 2007).
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
BENINI, LUCA;
2007
Abstract
Clustered sleep transistor insertion is an effective leakage power reduction technique that is well-suited for integration in an automated design flow and offers a flexible tradeoff between area, delay overhead and turn-on transition time. In this work, we focus on the design of a family of sleep transistor cells, fully compatible with the physical design rules of a commercial 65nm CMOS library. We describe circuit-level and layout optimizations, as well as the cell characterization procedure required to support automated sleep transistor cell selection and instantiation in a clustered power-gating insertion flow.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
