Modern computer vision and image processing embedded systems exploit hardware acceleration inside scalable parallel architectures, such as tightly-coupled clusters, to achieve stringent performance and energy efficiency targets. Architectural heterogeneity typically makes software development cumbersome, thus shared memory processor-to-accelerator communication is typically preferred to simplify code offioading to HW IPs for critical computational kernels. However, tightly coupling a large number of accelerators and processors in a shared memory cluster is a challenging task, since the complexity of the resulting system quickly becomes too large. We tackle these issues by proposing a template of heterogeneous shared memory cluster which scales to a large number of accelerators, achieving up to 40% better performance/area/watt than simply designing larger main interconnects to accommodate several HW IPs. In addition, following a trend towards standardization of acceleration capabilities of future embedded systems, we develop a programming model which simplifies application development for heterogeneous clusters.

Burgio P., Marongiu A., Danilo R., Coussy P., Benini L. (2013). Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters. IEEE 2013.

Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters

BURGIO, PAOLO;MARONGIU, ANDREA;BENINI, LUCA
2013

Abstract

Modern computer vision and image processing embedded systems exploit hardware acceleration inside scalable parallel architectures, such as tightly-coupled clusters, to achieve stringent performance and energy efficiency targets. Architectural heterogeneity typically makes software development cumbersome, thus shared memory processor-to-accelerator communication is typically preferred to simplify code offioading to HW IPs for critical computational kernels. However, tightly coupling a large number of accelerators and processors in a shared memory cluster is a challenging task, since the complexity of the resulting system quickly becomes too large. We tackle these issues by proposing a template of heterogeneous shared memory cluster which scales to a large number of accelerators, achieving up to 40% better performance/area/watt than simply designing larger main interconnects to accommodate several HW IPs. In addition, following a trend towards standardization of acceleration capabilities of future embedded systems, we develop a programming model which simplifies application development for heterogeneous clusters.
2013
Design and Architectures for Signal and Image Processing (DASIP), 2013 Conference on
22
29
Burgio P., Marongiu A., Danilo R., Coussy P., Benini L. (2013). Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters. IEEE 2013.
Burgio P.; Marongiu A.; Danilo R.; Coussy P.; Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/388145
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