Equalizing the ratios between workloads and speeds of processing elements provides the optimal speed allocation. Based on that principle, this work describes a dynamic speed setting policy for multiprocessor systems-on-chip (MPSoCs) that relies on the estimation of processor idle times specifically due to the synchronization work. The policy provides two advantages: first, it does not rely on any assumption about the communication pattern of the application executed by the system. Second, it is purely architectural; it automatically detects changes in the system workload and sets processors speeds accordingly by means of a custom hardware block.Results on a parallel MPEG video decoding application show an EDP saving above 55%, averaged over several datasets, corresponding to an energy saving above 50%, and a corresponding penalty in performance below 8%.

Synchronization-driven dynamic speed scaling for MPSoCs / M. Loghi; M. Poncino; L. Benini. - STAMPA. - (2006), pp. 346-349. (Intervento presentato al convegno Proceedings of the 2006 international symposium on Low power electronics and design tenutosi a Tegernsee, Bavaria, Germany nel 2006).

Synchronization-driven dynamic speed scaling for MPSoCs

BENINI, LUCA
2006

Abstract

Equalizing the ratios between workloads and speeds of processing elements provides the optimal speed allocation. Based on that principle, this work describes a dynamic speed setting policy for multiprocessor systems-on-chip (MPSoCs) that relies on the estimation of processor idle times specifically due to the synchronization work. The policy provides two advantages: first, it does not rely on any assumption about the communication pattern of the application executed by the system. Second, it is purely architectural; it automatically detects changes in the system workload and sets processors speeds accordingly by means of a custom hardware block.Results on a parallel MPEG video decoding application show an EDP saving above 55%, averaged over several datasets, corresponding to an energy saving above 50%, and a corresponding penalty in performance below 8%.
2006
Proceedings of the 2006 international symposium on Low power electronics and design. Tegernsee, Bavaria, Germany. POSTER SESSION: Low power mixed-signal and digital systems
346
349
Synchronization-driven dynamic speed scaling for MPSoCs / M. Loghi; M. Poncino; L. Benini. - STAMPA. - (2006), pp. 346-349. (Intervento presentato al convegno Proceedings of the 2006 international symposium on Low power electronics and design tenutosi a Tegernsee, Bavaria, Germany nel 2006).
M. Loghi; M. Poncino; L. Benini
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/34345
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