We propose a low-leakage cache architecture based on the observation of the spatio-temporal properties of data caches. In particular, we exploit the fact that during the program lifetime a few data values tend to exhibit both spatial and temporal locality in cache, i.e., values that are simultaneously stored by several lines at the same time. Leakage energy can be reduced by turning off those lines and storing these values in a smaller, separate memory. In this work we introduce an architecture that implements such a scheme, as well as an algorithm to detect these special values. We show that by using as few as four values we can achieve 18.45% leakage energy savings, with an additional 13.85% reduction of dynamic energy as a consequence of a reduced average cache access cost.

STV-Cache: a leakage energy-efficient architecture for data caches / K. Patel; L. Benini; E. Macii; M. Poncino. - STAMPA. - (2006), pp. 404-409. (Intervento presentato al convegno 16th ACM Great Lakes symposium on VLSI tenutosi a Philadelphia, PA, USA nel 2006).

STV-Cache: a leakage energy-efficient architecture for data caches

BENINI, LUCA;
2006

Abstract

We propose a low-leakage cache architecture based on the observation of the spatio-temporal properties of data caches. In particular, we exploit the fact that during the program lifetime a few data values tend to exhibit both spatial and temporal locality in cache, i.e., values that are simultaneously stored by several lines at the same time. Leakage energy can be reduced by turning off those lines and storing these values in a smaller, separate memory. In this work we introduce an architecture that implements such a scheme, as well as an algorithm to detect these special values. We show that by using as few as four values we can achieve 18.45% leakage energy savings, with an additional 13.85% reduction of dynamic energy as a consequence of a reduced average cache access cost.
2006
Proceedings of the 16th ACM Great Lakes symposium on VLSI. SESSION: System & architectural-level power optimization
404
409
STV-Cache: a leakage energy-efficient architecture for data caches / K. Patel; L. Benini; E. Macii; M. Poncino. - STAMPA. - (2006), pp. 404-409. (Intervento presentato al convegno 16th ACM Great Lakes symposium on VLSI tenutosi a Philadelphia, PA, USA nel 2006).
K. Patel; L. Benini; E. Macii; M. Poncino
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/31012
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