In this work we present a multi-path routing strategy that guaran-tees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to opti-mally spread the traffic in the NoC to minimize the network band-width needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large re-duction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip / S. Murali; D. Atienza; L. Benini; G. De Micheli. - STAMPA. - (2006), pp. 845-848. (Intervento presentato al convegno Annual ACM IEEE Design Automation Conference tenutosi a San Francisco, CA, USA nel 2006).

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

BENINI, LUCA;
2006

Abstract

In this work we present a multi-path routing strategy that guaran-tees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to opti-mally spread the traffic in the NoC to minimize the network band-width needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large re-duction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.
2006
Proceedings of the 43rd annual conference on Design automation table of contents. Session 49: analysis and optimization issues in NoC design
845
848
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip / S. Murali; D. Atienza; L. Benini; G. De Micheli. - STAMPA. - (2006), pp. 845-848. (Intervento presentato al convegno Annual ACM IEEE Design Automation Conference tenutosi a San Francisco, CA, USA nel 2006).
S. Murali; D. Atienza; L. Benini; G. De Micheli
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/30204
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