Memories are known to be the energy bottleneck of portable embedded devices. Numerous memory aware energy optimizations have been proposed. However, both the optimization and the validation are performed in an ad-hoc manner as a coherent optimizing compilation and simulation framework does not exist as yet. In this paper, we present such a framework for performing memory hierarchy aware energy optimization. Both the compiler and the simulator are configured from a single memory hierarchy description. Significant savings of up to 50% in the total energy dissipation are reported
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations / M. Verma; L. Wehmeyer; R. Pyka; P. Marwedel; L. Benini. - STAMPA. - (2006), pp. 279-288. (Intervento presentato al convegno Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop, SAMOS 2006. Proceedings tenutosi a Samos, Greece nel 17-20 July 2006).
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations
BENINI, LUCA
2006
Abstract
Memories are known to be the energy bottleneck of portable embedded devices. Numerous memory aware energy optimizations have been proposed. However, both the optimization and the validation are performed in an ad-hoc manner as a coherent optimizing compilation and simulation framework does not exist as yet. In this paper, we present such a framework for performing memory hierarchy aware energy optimization. Both the compiler and the simulator are configured from a single memory hierarchy description. Significant savings of up to 50% in the total energy dissipation are reportedI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
