We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results
A simulation-based power-aware architecture exploration of a multiprocessor System-on-Chip design / F. Menichelli; M. Olivieri; L. Benini; M. Donno; L. Bisdounis. - STAMPA. - (2004), pp. 312-317. (Intervento presentato al convegno 2004 Design, Automation and Test in Europe Conference and Exhibition tenutosi a Paris, France nel 16-20 February, 2004) [10.1109/DATE.2004.1269256].
A simulation-based power-aware architecture exploration of a multiprocessor System-on-Chip design
BENINI, LUCA;
2004
Abstract
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling resultsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
