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EnglishBarrier synchronization is a key programming primitive for shared memory embedded MPSoCs. As the core count increases, software implementations cannot provide the needed performance and scalability, thus making hardware acceleration critical. In this paper we describe an interconnect extension implemented with standard cells and with a mainstream industrial toolflow. We show that the area overhead is marginal with respect to the performance improvements of the resulting hardware-accelerated barriers.We integrate our HW barrier into the OpenMP programming model and discuss synchronization efficiency compared with traditional software implementations.
| Titolo: | Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs |
| Autore/i: | Abellan J. L.; Fernandez J.; Acacio M. E.; BERTOZZI, DAVIDE; BORTOLOTTI, DANIELE; MARONGIU, ANDREA; BENINI, LUCA |
| Autore/i Unibo: | |
| Anno: | 2012 |
| Titolo del libro: | Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 |
| Pagina iniziale: | 491 |
| Pagina finale: | 496 |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/DATE.2012.6176519 |
| Abstract: | Barrier synchronization is a key programming primitive for shared memory embedded MPSoCs. As the core count increases, software implementations cannot provide the needed performance and scalability, thus making hardware acceleration critical. In this paper we describe an interconnect extension implemented with standard cells and with a mainstream industrial toolflow. We show that the area overhead is marginal with respect to the performance improvements of the resulting hardware-accelerated barriers.We integrate our HW barrier into the OpenMP programming model and discuss synchronization efficiency compared with traditional software implementations. |
| Data prodotto definitivo in UGOV: | 26-giu-2013 |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11585/132663
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