Design and implementation of a novel multi-constellation FPGA-based dual frequency GNSS receiver for space applications

In the recent years, the use of GNSS receivers for on-board satellite orbit determination has become a common solution, as it considerably simplifies the overall architecture if compared to traditional orbit determination system such as radiometric tracking. Different challenges have to be faced while designing a GNSS system for this type of application, since in general the terrestrial receiver are not designed to guarantee their performances if placed in and orbital environment. The differences can be grouped in two main areas: the first is related to the signal properties, as higher signal strength variations, higher Doppler and Doppler rate must be accounted for, to design the proper acquisition and tracking strategy. The second group of differences is related to the space environment that affects the electronic systems in general trough severe temperature variation and the various types of radiations. These aspects are combined together in the design of a novel FPGA based GPS and Galileo receiver for space applications. This paper describes first the receiver requirements, that were defined trough simulations, using a GNSS full system and navigation software simulator, which provides also PVT accuracy estimation by the implementation of the navigation filter. The receiver hardware is based on the Xilinx FPGA, which incorporates a PowerPC in form of hard processor. The paper describes also the electronic hardware, together with the tracking algorithms, providing details about the combined third order PLL carrier aided DLL implementation. On-board navigation algorithms are also discussed with respect to the relevant error sources, showing that the achievable positioning accuracy provided by the simulator ranges from sub-meter for the dual frequency solution to one-three meters for the single frequency solution.