This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.

D. Rossi, C. Mucci, F. Campi, S. Spolzino, L. Vanzolini, H. Sahlbach, et al. (2013). Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21(2), 193-205 [10.1109/TVLSI.2012.2185963].

Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

ROSSI, DAVIDE;MUCCI, CLAUDIO;CAMPI, FABIO;GUERRIERI, ROBERTO
2013

Abstract

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.
2013
D. Rossi, C. Mucci, F. Campi, S. Spolzino, L. Vanzolini, H. Sahlbach, et al. (2013). Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21(2), 193-205 [10.1109/TVLSI.2012.2185963].
D. Rossi; C. Mucci; F. Campi; S. Spolzino; L. Vanzolini; H. Sahlbach; S. Whitty; R. Ernst; W. Putzke-Röming; R. Guerrieri
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/126393
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