Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-grained reconfigurable architectures offer higher computation density, but at the price of rather being domain specific. Programmability is also a major issue related to all of the described solutions. This paper describes a heterogeneous multi-core system-on-chip that exploits different flavours of reconfigurable computing, merged together in a high parallel on-chip and off-chip interconnect utilized for both data and configuration. The aim of this work is to deliver a single monolithic engine that capitalizes on the strong points of different reconfigurable fabrics, while providing a friendly programming interface. The user is ultimately able to manage a broad spectrum of different applications, exploiting the most efficient means of computation through utilization of each kernel, while retaining a software-oriented development environment as much as possible.

D. Rossi, F. Campi, A. Deledda, C. Mucci, S. Pucillo, S. Whitty, et al. (2009). A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing. s.l : IEEE [10.1109/SOCC.2009.5335668].

A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing

ROSSI, DAVIDE;DELEDDA, ANTONIO;
2009

Abstract

Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-grained reconfigurable architectures offer higher computation density, but at the price of rather being domain specific. Programmability is also a major issue related to all of the described solutions. This paper describes a heterogeneous multi-core system-on-chip that exploits different flavours of reconfigurable computing, merged together in a high parallel on-chip and off-chip interconnect utilized for both data and configuration. The aim of this work is to deliver a single monolithic engine that capitalizes on the strong points of different reconfigurable fabrics, while providing a friendly programming interface. The user is ultimately able to manage a broad spectrum of different applications, exploiting the most efficient means of computation through utilization of each kernel, while retaining a software-oriented development environment as much as possible.
2009
Proceedings of 2009 International Symposium on System-on-Chip
106
109
D. Rossi, F. Campi, A. Deledda, C. Mucci, S. Pucillo, S. Whitty, et al. (2009). A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing. s.l : IEEE [10.1109/SOCC.2009.5335668].
D. Rossi; F. Campi; A. Deledda; C. Mucci; S. Pucillo; S. Whitty; R. Ernst; S. Chevobbe; S. Guyetant; M. Kühnle; M. Hübner; J. Becker; W. Putzke-Roemin...espandi
File in questo prodotto:
Eventuali allegati, non sono esposti

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/115668
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 1
social impact