This paper describes a system on chip (SoC) implementation of a heterogeneous multi-core digital signal processor, that exploits different flavours of reconfigurable computing, merged together in a highly-parallel on chip interconnect utilized for data, configuration and control. The device incorporates an embedded field programmable gate array (eFPGA), a mid-grain intensive-computation reconfigurable datapath (DREAM), and a coarse grain reconfigurable array (PACT XPP) integrated on 3 independent clock islands. On a fourth global clock island an ARM processor manages communication, configuration and synchronization between the cores. The device joins the flexibility of the three heterogeneous run-time configurable engines together with the dynamic frequency scaling techniques enabling performance/power tuning. The SoC was implemented in 90 nm CMOS technology and is 110 mm2. It performs several GOP/S, depending on operation granularity.

A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing

ROSSI, DAVIDE;
2009

Abstract

This paper describes a system on chip (SoC) implementation of a heterogeneous multi-core digital signal processor, that exploits different flavours of reconfigurable computing, merged together in a highly-parallel on chip interconnect utilized for data, configuration and control. The device incorporates an embedded field programmable gate array (eFPGA), a mid-grain intensive-computation reconfigurable datapath (DREAM), and a coarse grain reconfigurable array (PACT XPP) integrated on 3 independent clock islands. On a fourth global clock island an ARM processor manages communication, configuration and synchronization between the cores. The device joins the flexibility of the three heterogeneous run-time configurable engines together with the dynamic frequency scaling techniques enabling performance/power tuning. The SoC was implemented in 90 nm CMOS technology and is 110 mm2. It performs several GOP/S, depending on operation granularity.
2009
Proceedings of IEEE Custom Integrated Circuit Conference
641
644
D.Rossi; F.Campi; A.Deledda; S.Spolzino; S.Pucillo
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/115667
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