This paper describes the implementation of a floating-point matrix-vector multiplication on a reconfigurable system. The matrix-vector multiplication is meant to be used to perform two steps (transformation and perspective projection) of a 3D graphics application. The target system is based on a bus architecture with a general purpose core as master and the reconfigurable array as main accelerator. The system has been prototyped on a FPGA device. The matrix-vector multiplication has been successfully implemented on the reconfigurable block. Compared to the general purpose implementation it is convenient if the number of vectors to process is higher than seven. If hundreds of vectors are processed, the speed-up achievable reaches 3times.

F. Garzia, C. Brunelli, D. Rossi, J. Nurmi (2008). Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. s.l : IEEE [10.1109/IPDPS.2008.4536538].

Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture

ROSSI, DAVIDE;
2008

Abstract

This paper describes the implementation of a floating-point matrix-vector multiplication on a reconfigurable system. The matrix-vector multiplication is meant to be used to perform two steps (transformation and perspective projection) of a 3D graphics application. The target system is based on a bus architecture with a general purpose core as master and the reconfigurable array as main accelerator. The system has been prototyped on a FPGA device. The matrix-vector multiplication has been successfully implemented on the reconfigurable block. Compared to the general purpose implementation it is convenient if the number of vectors to process is higher than seven. If hundreds of vectors are processed, the speed-up achievable reaches 3times.
2008
Proceedings of IEEE International Symposium on Parallel & Distributed Processing, 2008. IPDPS 2008.
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F. Garzia, C. Brunelli, D. Rossi, J. Nurmi (2008). Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. s.l : IEEE [10.1109/IPDPS.2008.4536538].
F. Garzia; C. Brunelli; D. Rossi; J. Nurmi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/115660
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