This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.
Y. Sun, H.Y. Yu, N. Singh, T.T. Le, E. Gnani, G. Baccarani, et al. (2011). Junctionless stackable SONOS memory realized on vertical-Si-nanowire for 3-D application. HSINCHU : IEEE [10.1109/VTSA.2011.5872271].
Junctionless stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
GNANI, ELENA;BACCARANI, GIORGIO;
2011
Abstract
This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
