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EnglishThis work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.
| Titolo: | Junctionless stackable SONOS memory realized on vertical-Si-nanowire for 3-D application | |
| Autore/i: | Y. Sun; H. Y. Yu; N. Singh; T. T. Le; GNANI, ELENA; BACCARANI, GIORGIO; K. C. Leong; G. Q. Lo; D. L. Kwong | |
| Autore/i Unibo: | ||
| Anno: | 2011 | |
| Titolo del libro: | 18th International Symposium on VLSI Technology, Systems and Applications | |
| Pagina iniziale: | 1 | |
| Pagina finale: | 2 | |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/VTSA.2011.5872271 | |
| Abstract: | This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application. | |
| Data prodotto definitivo in UGOV: | 26-giu-2013 | |
| Appare nelle tipologie: | 4.02 Riassunto (Abstract) |
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