This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.

Junctionless stackable SONOS memory realized on vertical-Si-nanowire for 3-D application

GNANI, ELENA;BACCARANI, GIORGIO;
2011

Abstract

This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS < 70 mV/dec, leakage current < 1 pA and a memory window of 3.2 V with 1 ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.
18th International Symposium on VLSI Technology, Systems and Applications
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Y. Sun; H.Y. Yu; N. Singh; T.T. Le; E. Gnani; G. Baccarani; K.C. Leong; G.Q. Lo; D.L. Kwong
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/106881
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