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EnglishThree dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floor planner. Our experiments on many SoC benchmarks show a reduction of 8 - 10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches.
| Titolo: | A Method for Integrating Network-on-Chip Topologies with 3D ICs | |
| Autore/i: | M. Pawan Kumar; A. S. Kumar; S. Murali; BENINI, LUCA; K. Veezhinathan | |
| Autore/i Unibo: | ||
| Anno: | 2011 | |
| Titolo del libro: | 2011 IEEE Computer Society Annual Symposium on VLSI | |
| Pagina iniziale: | 60 | |
| Pagina finale: | 65 | |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/ISVLSI.2011.74 | |
| Abstract: | Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floor planner. Our experiments on many SoC benchmarks show a reduction of 8 - 10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches. | |
| Data prodotto definitivo in UGOV: | 27-giu-2013 | |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11585/106071
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