Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floor planner. Our experiments on many SoC benchmarks show a reduction of 8 - 10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches.
M. Pawan Kumar, A. S. Kumar, S. Murali, L. Benini, K. Veezhinathan (2011). A Method for Integrating Network-on-Chip Topologies with 3D ICs. NEW YORK : IEEE Press [10.1109/ISVLSI.2011.74].
A Method for Integrating Network-on-Chip Topologies with 3D ICs
BENINI, LUCA;
2011
Abstract
Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floor planner. Our experiments on many SoC benchmarks show a reduction of 8 - 10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
