Current embedded computing architectures are moving to many-core concepts in order to sustain ever growing computing requirements within complexity and power budgets. Programming many-core architectures not only needs parallel programming skills, but also efficient exploitation of the parallelism at both the architecture and runtime levels. This paper presents a reactive tasks management (RTM) technique that is suitable for fine grain parallelism. Exploiting fine-grain parallelism eases the work of the developer since, most of the time, it is a form of parallelism which is naturally present in applications and doesn't require heavy algorithm rewriting. The RTM API leverages both hardware and software support to efficiently exploit fine-grain parallelism at the lowest possible cost. Simulation on the VC-1 decoding application showed that only 3.5% overhead is induced by this API which makes it truly suitable for fine grain tasks scheduling.

Synchronous Reactive Fine Grain Tasks Management for Homogeneous Many-Core Architectures

BENINI, LUCA
2011

Abstract

Current embedded computing architectures are moving to many-core concepts in order to sustain ever growing computing requirements within complexity and power budgets. Programming many-core architectures not only needs parallel programming skills, but also efficient exploitation of the parallelism at both the architecture and runtime levels. This paper presents a reactive tasks management (RTM) technique that is suitable for fine grain parallelism. Exploiting fine-grain parallelism eases the work of the developer since, most of the time, it is a form of parallelism which is naturally present in applications and doesn't require heavy algorithm rewriting. The RTM API leverages both hardware and software support to efficiently exploit fine-grain parallelism at the lowest possible cost. Simulation on the VC-1 decoding application showed that only 3.5% overhead is induced by this API which makes it truly suitable for fine grain tasks scheduling.
ARCS 2011, 24th International Conference on Architecture of Computing Systems 2011, Workshop Proceedings
144
150
Ojail M.; David R.; Chehida K.B.; Lhuillier Y. (CEA, France); Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/105327
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