Nanowatt clock and data recovery for ultra-low power wake-up receivers

This paper presents the design of a data-startable baseband logic for wake-up receivers (WuRxs) enabling nodes to receive infinite bits in addition to a codeword. The proposed integrated circuit includes a control logic with addressing capabilities and a clock and data recovery (CDR) block based on a Gated Oscillator (GO). At each data transition the phase misalignment between received data and clock is compensated in a highly energy-efficient way thus allowing to correctly receive infinite bits. The difference between the Gated Oscillator free-running frequency and the bit-rate limits only the maximum number of equal consecutive bits that can be received. A design is presented in STMicroelectronics 90-nm BCD technology 1.2-V supply. Baseband logic has been supplied with 0.6 V to reduce overall consumption. The overall power consumption is 4.78 nW during the rest state and 9 pJ/bit at 1-kbps data rate. The CDR circuit alone consumes 0.162 nW during the rest state and 4.23 nW in active state that results in 4.23 pJ/bit at 1-kbps data rate.