Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%–30.15% accuracy for 427 × –137,682 × speedup.
Iff, P., Bruggmann, B., Morel, B., Besta, M., Benini, L., Hoefler, T. (2025). RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects [10.1145/3719276.3725170].
RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects
Benini, Luca;
2025
Abstract
Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%–30.15% accuracy for 427 × –137,682 × speedup.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
