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A semiautomated, fast turnaround, and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices. © 1993 IEEE

Blythe, S., Fraboni, B., Lall, S., Ahmed, H. (1993). Layout Reconstruction of Complex Silicon Chips. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 28(2), 138-145 [10.1109/4.192045].

Layout Reconstruction of Complex Silicon Chips

Fraboni B.;
1993

Abstract

A semiautomated, fast turnaround, and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices. © 1993 IEEE
1993
Blythe, S., Fraboni, B., Lall, S., Ahmed, H. (1993). Layout Reconstruction of Complex Silicon Chips. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 28(2), 138-145 [10.1109/4.192045].
Blythe, S.; Fraboni, B.; Lall, S.; Ahmed, H.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/1001752
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