In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical electromagnetic-interference reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional aperiodic modulating signal is used, the clock can be recovered by exploiting a standard clock and data recovery circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13- m CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps , while the chip active area is mm and the power consumption is as low as 14.7 mW.

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

PARESCHI, FABIO;ROVATTI, RICCARDO
2010

Abstract

In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical electromagnetic-interference reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional aperiodic modulating signal is used, the clock can be recovered by exploiting a standard clock and data recovery circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13- m CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps , while the chip active area is mm and the power consumption is as low as 14.7 mW.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/98416
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