This paper presents a subthreshold capacitorless low-dropout (LDO) voltage regulator for powering a Wake-Up Receiver (WuRX) in an ultra-low power IoT system. The system must maintain very low quiescent current to maximize the battery life of the node. Since the standby power consumption of the reference wake-up circuit is extremely low (< 55 nW), it is crucial that the LDO has even lower power consumption to avoid becoming the bottleneck of the entire system. The proposed LDO maintains a power consumption below 5 nW across the entire possible input voltage range from 0.7 V to 4.2 V, which includes the typical voltage range of lithium batteries. In nominal condition, with input voltage of 1.2 V, the power consumption is only 803 pW, accounting for less than 2% of the entire node. Circuit design was performed on an STMicroelectronics 90-nm CMOS technology and achieve low output voltage ripple in presence of the current profiles requested by the WuRX load, and temperature stability, while maintaining the above power consumption across possible process and temperature variations. Additionally, a transistor-level simulation of the entire circuit consisting of LDO and WuRX is reported, to demonstrate the correct functionality of the whole system.
Villa Marco, Guerrini Marco, Franchi Scarselli Eleonora, D'Addato Matteo, Elgani A.M., Nicolosi Alessandro, et al. (2024). Design of a Nano-Power Capacitor-Less LDO Voltage Regulator for Wake-Up Radio Applications. IEEE [10.1109/PRIME61930.2024.10559700].
Design of a Nano-Power Capacitor-Less LDO Voltage Regulator for Wake-Up Radio Applications
Villa Marco;Guerrini Marco;Franchi Scarselli Eleonora;Romani Aldo
2024
Abstract
This paper presents a subthreshold capacitorless low-dropout (LDO) voltage regulator for powering a Wake-Up Receiver (WuRX) in an ultra-low power IoT system. The system must maintain very low quiescent current to maximize the battery life of the node. Since the standby power consumption of the reference wake-up circuit is extremely low (< 55 nW), it is crucial that the LDO has even lower power consumption to avoid becoming the bottleneck of the entire system. The proposed LDO maintains a power consumption below 5 nW across the entire possible input voltage range from 0.7 V to 4.2 V, which includes the typical voltage range of lithium batteries. In nominal condition, with input voltage of 1.2 V, the power consumption is only 803 pW, accounting for less than 2% of the entire node. Circuit design was performed on an STMicroelectronics 90-nm CMOS technology and achieve low output voltage ripple in presence of the current profiles requested by the WuRX load, and temperature stability, while maintaining the above power consumption across possible process and temperature variations. Additionally, a transistor-level simulation of the entire circuit consisting of LDO and WuRX is reported, to demonstrate the correct functionality of the whole system.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.