FPGA implementation of a wavelet-based algorithm for real-time signal detection and denoising

In this work we present two Field Programmable Gate Array (FPGA) implementations of an algorithm for signal detection and denoising based on undecimated (Stationary) Wavelet Packet Transform (SWPT). The former exploits the symmetry of the orthogonal filters used in the wavelet transformation, the latter is based on lifting scheme. Both the architectures are easily reconfigurable and able to redirect the analysis to different wavelet packet domains performing a real-time analysis. We considered filter coefficients quantization and finite word length effects in order to limit the signal-to-noise ratio (SNR) penalty, due to quantization noise, in the hardware implementation, obtaining good matching between FPGA and floating point simulation. Hardware performances are provided together with the simulation results.