Editor's notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer's manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision.-Vivek Chickermane, Cadence

Victor Jimenez, Mario Rodriguez, Marc Dominguez, Josep Sans, Ivan Diaz, Luca Valente, et al. (2022). Functional Verification of a {RISC}-V Vector Accelerator. IEEE DESIGN & TEST, 40(3), 36-44 [10.1109/mdat.2022.3226709].

Functional Verification of a {RISC}-V Vector Accelerator

Luca Valente;
2022

Abstract

Editor's notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer's manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision.-Vivek Chickermane, Cadence
2022
Victor Jimenez, Mario Rodriguez, Marc Dominguez, Josep Sans, Ivan Diaz, Luca Valente, et al. (2022). Functional Verification of a {RISC}-V Vector Accelerator. IEEE DESIGN & TEST, 40(3), 36-44 [10.1109/mdat.2022.3226709].
Victor Jimenez; Mario Rodriguez; Marc Dominguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehi...espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/952944
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