Editor's notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer's manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision.-Vivek Chickermane, Cadence
Functional Verification of a {RISC}-V Vector Accelerator / Victor Jimenez; Mario Rodriguez; Marc Dominguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sonmez; Oscar Palomar; Miquel Moreto. - In: IEEE DESIGN & TEST. - ISSN 2168-2356. - ELETTRONICO. - 40:3(2022), pp. 36-44. [10.1109/mdat.2022.3226709]
Functional Verification of a {RISC}-V Vector Accelerator
Luca Valente;
2022
Abstract
Editor's notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer's manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision.-Vivek Chickermane, CadenceI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
