This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. Optical packets are assembled by aggregating IP packets, and attaching an optical packet header. Conventional schemes process optical packet headers one by one, in a sequential form. Then, worst case algorithm response time is tightly coupled to switch size. In contrast, in PI-OPS all the optical packets received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques. The scheduler has a deterministic response time, independent of the traffic arrivals pattern. In addition, PI-OPS has been specifically designed to allow a parallel electronic implementation similar to the ones found in VOQ schedulers. In this respect, we evaluate the traffic loss performance of the scheduler in different settings, to dimension a set of hardware related parameters. Finally, we conduct an emulation of an FPGA implementation of a large-scale version of the scheduler. Results support the feasibility of its implementation.

A parallel iterative scheduler for asynchronous Optical Packet Switching networks

CERRONI, WALTER;CAMPI, ALDO;CALLEGATI, FRANCO
2011

Abstract

This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. Optical packets are assembled by aggregating IP packets, and attaching an optical packet header. Conventional schemes process optical packet headers one by one, in a sequential form. Then, worst case algorithm response time is tightly coupled to switch size. In contrast, in PI-OPS all the optical packets received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques. The scheduler has a deterministic response time, independent of the traffic arrivals pattern. In addition, PI-OPS has been specifically designed to allow a parallel electronic implementation similar to the ones found in VOQ schedulers. In this respect, we evaluate the traffic loss performance of the scheduler in different settings, to dimension a set of hardware related parameters. Finally, we conduct an emulation of an FPGA implementation of a large-scale version of the scheduler. Results support the feasibility of its implementation.
P. Pavon-Marino; M. Bueno-Delgado; W. Cerroni; A. Campi; F. Callegati
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/93017
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