Efficiency and readout architectures for a large matrix of pixels

We present a digital readout architecture for a silicon pixel matrix sensor. It has been developed to cope with high hit rates, above 1 MHz/mm2 for matrices greater than 80K pixels. This technology can be implemented inside a silicon MAPS device (Monolithic Active Pixel Sensor): a high resolution particle detector which integrates on the same bulk the sensor matrix and the CMOS logic for readout. The architecture proposed is based on three main concepts. In first place the readout of the hits is performed by activating one column at a time; all the fired pixels on the active column are read, sparsified and reset in parallel in one clock cycle. This implies the use of global signals across the sensor matrix, the consequent reduction of metal interconnections improves the active area while maintaining a high granularity (down to 40 mm of pixel pitch). Secondly, the activation for readout takes place only for those columns overlapping with a certain fired area, thus reducing the sweeping time of the whole matrix and reducing the pixel dead-time. Third, the sparsification (x-y address labeling of the hits) is performed with a lower granularity respect to single pixels, by addressing vertical zones of 8 pixels each. The fine-grain Y resolution is achieved by appending the zone pattern to the zone address of a hit. We show the benefits of this technique in presence of clusters. The main features of the readout architecture are described, then we presents the results obtained with a simulation of the VHDL readout model.