The SuperB Silicon Vertex Tracker

In the current design of the high luminosity SuperB asymmetric e+-e- collider, the center of mass boost is reduced with respect to BaBar and to efficiently perform the time-dependent measurements an improved vertex resolution is required. A vertex tracker based on the layout of the BaBar Silicon Vertex Tracker (SVT) with an additional innermost layer (Layer0) is a design that achieves such a tracking resolution, provided that the extra layer is placed at radius of 1.5 cm from the interaction point, its thickness is less than 1% X0 and it is able to withstand a background rate of several MHz/cm2. The different options for the Layer0 are reviewed, starting from the most technologically mature solution, a high resistivity short strip detector, describing then a smallpitch hybrid pixel detector and finally presenting the most challenging proposal, based on CMOS MAPS.