A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of a 256-pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect face-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic uses one layer that will be stacked on a sensor layer at the end of the fabrication process.

A. Gabrielli, F. Giorgi, M Villa, F. Morsani (2010). Fast readout logic interfacing a 256-pixel matrix of a dual-layer 3D device [10.1088/1748-0221/5/07/C07005].

Fast readout logic interfacing a 256-pixel matrix of a dual-layer 3D device

GABRIELLI, ALESSANDRO;GIORGI, FILIPPO MARIA;VILLA, MAURO;
2010

Abstract

A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of a 256-pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect face-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic uses one layer that will be stacked on a sensor layer at the end of the fabrication process.
2010
c07005
c07005-5
A. Gabrielli, F. Giorgi, M Villa, F. Morsani (2010). Fast readout logic interfacing a 256-pixel matrix of a dual-layer 3D device [10.1088/1748-0221/5/07/C07005].
A. Gabrielli; F. Giorgi; M Villa; F. Morsani
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/91734
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