The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 × 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130nm CMOS technology. The pixel dimension is 50 by 50 µm2. The work is aimed at improving the design of MAPS detectors with an onchip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.
A. Gabrielli, G. Batignani, S. Bettarini, F. Bosi, G. Calderini, R. Cenci, et al. (2009). On-chip fast data sparsification for a monolithic 4096-pixel device. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 56, 1159-1162 [10.1109/TNS.2008.2005497].
On-chip fast data sparsification for a monolithic 4096-pixel device
GABRIELLI, ALESSANDRO;DI SIPIO, RICCARDO;GIACOBBE, BENEDETTO;GIORGI, FILIPPO MARIA;SEMPRINI CESARI, NICOLA;SBARRA, CARLA;SPIGHI, ROBERTO;VALENTINETTI, SARA;VILLA, MAURO;ZOCCOLI, ANTONIO
2009
Abstract
The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 × 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130nm CMOS technology. The pixel dimension is 50 by 50 µm2. The work is aimed at improving the design of MAPS detectors with an onchip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
