Plugging an IP core into an embedded platform implies the generation of a device driver complying with the IP communication protocol from one side and with the CPU organization (i.e., single processor, SMP, AMP) from the other side. Reusing an existent driver developed for a different CPU organization needs a time-consuming and error-prone manual customization of it, that discourages the evaluation of alternative target platform organizations. In this context, the paper firstly proposes to extract the formal model of the IP communication protocol from the RTL testbench provided with it. Then a taxonomy of device drivers is presented based on the CPU organization of the platform. This taxonomy allows to select the correct template used to automatically generate a device driver compliant with the CPU organization, with the use in a simulated or in a real platform, with the interrupt support, with the operating system, with the I/O architecture and with the possible parallel execution. The proposed methodology has been successfully tested on a family of embedded platforms with different CPU organizations.

Automatic Customization of Device Drivers for IP-cores Used with Assorted CPU Organizations

ACQUAVIVA, ANDREA;
2009

Abstract

Plugging an IP core into an embedded platform implies the generation of a device driver complying with the IP communication protocol from one side and with the CPU organization (i.e., single processor, SMP, AMP) from the other side. Reusing an existent driver developed for a different CPU organization needs a time-consuming and error-prone manual customization of it, that discourages the evaluation of alternative target platform organizations. In this context, the paper firstly proposes to extract the formal model of the IP communication protocol from the RTL testbench provided with it. Then a taxonomy of device drivers is presented based on the CPU organization of the platform. This taxonomy allows to select the correct template used to automatically generate a device driver compliant with the CPU organization, with the use in a simulated or in a real platform, with the interrupt support, with the operating system, with the I/O architecture and with the possible parallel execution. The proposed methodology has been successfully tested on a family of embedded platforms with different CPU organizations.
2009
Proceedings of International conference on Hardware/Software Co-Design
173
182
ACQUAVIVA, ANDREA; BOMBIERI N; FUMMI F; VINCO, SARA
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/833302
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