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EnglishA prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process.
| Titolo: | An on-Chip Fast Readout Sparsification for a 256-Pixel 3D Device |
| Autore/i: | GABRIELLI, ALESSANDRO; GIORGI, FILIPPO MARIA; VILLA, MAURO; F. Morsani |
| Autore/i Unibo: | |
| Anno: | 2009 |
| Titolo del libro: | Conference Publication: 2009 Nuclear Science Symposium and Medical Imaging Conference |
| Pagina iniziale: | 1158 |
| Pagina finale: | 1160 |
| Digital Object Identifier (DOI): | 10.1109/NSSMIC.2009.5402396 |
| Abstract: | A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process. |
| Data prodotto definitivo in UGOV: | 18-feb-2010 |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11585/80477
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