A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process.
A. Gabrielli, F. Giorgi, M. Villa, F. Morsani (2009). An on-Chip Fast Readout Sparsification for a 256-Pixel 3D Device. Orlando : IEEE [10.1109/NSSMIC.2009.5402396].
An on-Chip Fast Readout Sparsification for a 256-Pixel 3D Device
GABRIELLI, ALESSANDRO;GIORGI, FILIPPO MARIA;VILLA, MAURO;
2009
Abstract
A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
