An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear combination of consecutive signal samples, as required by the CS encoding. To manage the presence of leakage currents, which may impair signal reconstruction, a compensation circuit is considered, allowing close-to-ideal performance of the system when properly designed. A neural network-based decoding strategy is also analyzed, with up to 20 dB of additional reconstruction quality with respect to standard algorithms. Synthetic electrocardiogram signals are used to validate optimizations both at the hardware level in the encoding block and at the software level in the decoder.

A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC

Mangia M.;Rovatti R.;
2020

Abstract

An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear combination of consecutive signal samples, as required by the CS encoding. To manage the presence of leakage currents, which may impair signal reconstruction, a compensation circuit is considered, allowing close-to-ideal performance of the system when properly designed. A neural network-based decoding strategy is also analyzed, with up to 20 dB of additional reconstruction quality with respect to standard algorithms. Synthetic electrocardiogram signals are used to validate optimizations both at the hardware level in the encoding block and at the software level in the decoder.
Paolino C.; Prono L.; Pareschi F.; Mangia M.; Rovatti R.; Setti G.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/763410
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