Extraction of an Extrinsic Parasitic Network for Accurate mm-Wave FET Scalable Modeling on the Basis of Full-Wave EM Simulation

This paper describes a new methodology for the extraction of an extrinsic parasitic network suitable for scalable electron device models. The extraction procedure is based on the data obtained through Full-Wave Electro-Magnetic (FW-EM) analyses of the passive structure of a reference device. The new topology proposed proves to be scalable according to simple linear rules derived from geometric considerations. This new parasitic network is used together with a scalable intrinsic device model in order to predict the behavior of different 0.25 μm GaAs PHEMTs (total gate-widths between 300 and 900 μm) belonging to a standard process for millimeter-wave applications. Better accuracy with respect to conventional modeling approaches, is proved up to 80 GHz.