This paper proposes a new strategy to achieve balanced capacitor voltages in modular multilevel converters. Among the possible solutions, centralized arm control approaches are often adopted. These methods require a balancing technique based on a sorted list of the sub-modules according to their capacitor voltages. In order to achieve the aforementioned sorted list, different algorithms have been proposed in literature, such as: Sorting algorithms, max/min approaches, etc. However, the sorting algorithms require a long execution time, while the max/min approaches affect the converter dynamic response during faults. To overcome these issues, a new mapping strategy providing a quasi-sorted list is proposed in this paper. The suggested method is compared in simulation with both the classical bubble sorting algorithm, and the max/min method during both normal and faulty conditions. Moreover, the three methods have been implemented in a Xilinx Zynq-7000 System-on-Chip (SoC) device, in order to analyze the corresponding execution time and the required computational effort. Hardware-in-the-loop results are presented for demonstrating the superior performance of the proposed balancing strategy.

A capacitor voltage balancing approach based on mapping strategy for MMC applications

Ricco M.;Hammami M.
;
Rossi C.;
2019

Abstract

This paper proposes a new strategy to achieve balanced capacitor voltages in modular multilevel converters. Among the possible solutions, centralized arm control approaches are often adopted. These methods require a balancing technique based on a sorted list of the sub-modules according to their capacitor voltages. In order to achieve the aforementioned sorted list, different algorithms have been proposed in literature, such as: Sorting algorithms, max/min approaches, etc. However, the sorting algorithms require a long execution time, while the max/min approaches affect the converter dynamic response during faults. To overcome these issues, a new mapping strategy providing a quasi-sorted list is proposed in this paper. The suggested method is compared in simulation with both the classical bubble sorting algorithm, and the max/min method during both normal and faulty conditions. Moreover, the three methods have been implemented in a Xilinx Zynq-7000 System-on-Chip (SoC) device, in order to analyze the corresponding execution time and the required computational effort. Hardware-in-the-loop results are presented for demonstrating the superior performance of the proposed balancing strategy.
Ricco M.; Mathe L.; Hammami M.; Franco F.L.; Rossi C.; Teodorescu R.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/708291
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