Short-range process variations such as line-edge roughness (LER) and random dopant fluctuations (RD) are extremely critical in aggressively scaled devices. In this work, techniques to incorporate such variations into Technology Computer-Aided Design (TCAD) simulations are discussed. Different statistical approaches are considered, including Monte Carlo and propagation of variance techniques, which allow predicting the impact of process variations on both device and circuit performance through physical, mixed-mode and SPICE simulations. Statistical dependencies and correlations among fluctuations of several parameters are investigated to provide a link between physical-, device- and circuit-level modeling. The described techniques are exploited to investigate feasibility of mainstream applications of FinFET devices at the LSTP-32nm node. The performance of single devices and SRAM cells are characterized, comparing different contributions to line-edge roughness, assessing relative importance of LER and RD issues and providing design guidelines for minimizing the impact of short-range variations.
TCAD modeling and characterization of short-range variations in Multiple-Gate devices and circuit blocks / E. Baravelli; N. Speciale; A. Dixit; M. Jurczak. - STAMPA. - (2008), pp. 85-90. (Intervento presentato al convegno 15th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2008) tenutosi a Poznan, Poland nel June 19-21, 2008).
TCAD modeling and characterization of short-range variations in Multiple-Gate devices and circuit blocks
BARAVELLI, EMANUELE;SPECIALE, NICOLO'ATTILIO;
2008
Abstract
Short-range process variations such as line-edge roughness (LER) and random dopant fluctuations (RD) are extremely critical in aggressively scaled devices. In this work, techniques to incorporate such variations into Technology Computer-Aided Design (TCAD) simulations are discussed. Different statistical approaches are considered, including Monte Carlo and propagation of variance techniques, which allow predicting the impact of process variations on both device and circuit performance through physical, mixed-mode and SPICE simulations. Statistical dependencies and correlations among fluctuations of several parameters are investigated to provide a link between physical-, device- and circuit-level modeling. The described techniques are exploited to investigate feasibility of mainstream applications of FinFET devices at the LSTP-32nm node. The performance of single devices and SRAM cells are characterized, comparing different contributions to line-edge roughness, assessing relative importance of LER and RD issues and providing design guidelines for minimizing the impact of short-range variations.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
