Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal control is required because of temperature impact on leakage and reliability. To be effective, the implementation of these policies involves decisions that must be taken during various phases along the design process, to enable the development of architectural level countermeasures and the required hardware knobs, such as power modes, power supply regulation granularity and the number of on-chip temperature sensors. As a consequence, a framework allowing thermal estimation exploiting design-time information is desirable. In this paper we propose a solution on this direction, by presenting an integrated estimation environment for the evaluation of chip temperature profiles. It exploits heterogeneous power information available during the design phase. Power information is used to drive a thermal simulation engine capable of temperature feedback for the emulation of on-chip sensors. The framework has been demonstrated on an industrial case study, namely the ST SPEAr1300 embedded platform. Experimental results show how the proposed framework can be used to evaluate the temperature of a single component in isolation and also the effect on the temperature profile of the interactions among chip components depending on their power states. Finally we demonstrate the effect of temperature feedback on leakage power consumption.
ACQUAVIVA, A., CALIMERA, A., MACII, A., PONCINO, M., MACII, E., Giaconia M., et al. (2010). An integrated thermal estimation framework for industrial embedded platforms. ACM [10.1145/1785481.1785550].
An integrated thermal estimation framework for industrial embedded platforms
ACQUAVIVA, ANDREA;
2010
Abstract
Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal control is required because of temperature impact on leakage and reliability. To be effective, the implementation of these policies involves decisions that must be taken during various phases along the design process, to enable the development of architectural level countermeasures and the required hardware knobs, such as power modes, power supply regulation granularity and the number of on-chip temperature sensors. As a consequence, a framework allowing thermal estimation exploiting design-time information is desirable. In this paper we propose a solution on this direction, by presenting an integrated estimation environment for the evaluation of chip temperature profiles. It exploits heterogeneous power information available during the design phase. Power information is used to drive a thermal simulation engine capable of temperature feedback for the emulation of on-chip sensors. The framework has been demonstrated on an industrial case study, namely the ST SPEAr1300 embedded platform. Experimental results show how the proposed framework can be used to evaluate the temperature of a single component in isolation and also the effect on the temperature profile of the interactions among chip components depending on their power states. Finally we demonstrate the effect of temperature feedback on leakage power consumption.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.