A Low-Noise Amplifier for ultra wide band (UWB) applications is presented. The use of a dual-loop negative feedback topology is advantageous, since it allows to achieve both impedance matching and a very low noise figure, and saves a lot of chip area as no bulky inductors are needed. A nullor and a resistive feedback network are employed, and the values of the feedback elements involved are defined in order to fulfill the noise-figure, input impedance and power-gain requirements for an UWB receiver. To ensure circuit stability, frequency compensation is done by means of a phantom zero and the addition of a transistor connected between input and output, thus realizing a multipath structure. The design targets UMC 0.13μm CMOS IC technology and operation from a 1.2-volt supply. From circuit simulations, the power gain of the LNA amounts to 17dB, and the bandwidth spans up to 12GHz. S11 is below -10dB up to 10GHz and the noise figure is below 3dB up to 8GHz, and below 4dB@10GHz. The power consumption equals 14mA. Compared to competitive solutions, using resonating load stages or LC ladder networks, this chip will be much smaller and cheaper; it will use standard CMOS technology, and achieve very low noise, high gain and wide band matching at reasonable power consumption. ©2008 IEEE.

A UWB CMOS 0.13μm low-noise amplifier with dual loop negative feedback

DE MICHELE, LUCA ANTONIO;ROVATTI, RICCARDO
2008

Abstract

A Low-Noise Amplifier for ultra wide band (UWB) applications is presented. The use of a dual-loop negative feedback topology is advantageous, since it allows to achieve both impedance matching and a very low noise figure, and saves a lot of chip area as no bulky inductors are needed. A nullor and a resistive feedback network are employed, and the values of the feedback elements involved are defined in order to fulfill the noise-figure, input impedance and power-gain requirements for an UWB receiver. To ensure circuit stability, frequency compensation is done by means of a phantom zero and the addition of a transistor connected between input and output, thus realizing a multipath structure. The design targets UMC 0.13μm CMOS IC technology and operation from a 1.2-volt supply. From circuit simulations, the power gain of the LNA amounts to 17dB, and the bandwidth spans up to 12GHz. S11 is below -10dB up to 10GHz and the noise figure is below 3dB up to 8GHz, and below 4dB@10GHz. The power consumption equals 14mA. Compared to competitive solutions, using resonating load stages or LC ladder networks, this chip will be much smaller and cheaper; it will use standard CMOS technology, and achieve very low noise, high gain and wide band matching at reasonable power consumption. ©2008 IEEE.
Proceedings - IEEE International Symposium on Circuits and Systems
672
675
De Michele, Luca Antonio; Serdijn, Wouter A.; Bagga, Sumit; Setti, Gianluca; Rovatti, Riccardo
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/562423
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