Impact of Processing Conditions on the Level Scheme of Silicon Nanowires Synthesized by Top-Down Techniques

Massive and reliable synthesis of semiconductor NWs is an essential pre-requisite for the stepping out from the proof-of-concept stage towards real-world manufacturing of NW-based devices. In this respect it becomes of main concern to answer the question of how growth conditions could introduce point and/or extended defects into NW inner structures, mirroring themselves into the NW level schemes, and finally affecting NW-based device performances. We report here on the investigation of electrically active defects of Si NWs fabricated by two different top-down techniques, Reactive Ion Etching (RIE) [1] (Fig. 1a) and Metal-Assisted wet Chemical Etching (MaCE) [2] (Fig1b), by means of Deep Level Transient Spectroscopy (DLTS). Our studies reveal the existence of intra-gap levels induced during the Si NWs growth in both cases. We discuss their origin in cross-reference with the different physical mechanisms underlying the samples’ processing features. Differently from the case of MaCE Si NWs, the low density of RIE etched Si NWs has led us to develop a procedure in order to realize the Schottky barrier junction which is the conditio-sine-qua-non for performing DLTS characterization. Since the same procedure can be adopted for DLTS-probing of NW arrays under every density condition, this in turn opens the way to the systematic study of electrically active defects in semiconductor NWs by means of the sophisticated DLTS technique, of far-reaching consequence about defect characterization in semiconductor NWs. [1] S. Leopold et al., J. Vac. Sci. Technol. B, 29, 011002 (2011). [2] A. Irrera et al., Nanotechnology, 23, 075204 (2012).