CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 mm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN.
Design, Realization and Test of a Rad-Hard 2D-compressor and Packing Chip for High Energy Physics Experiments / A. Gabrielli; E. Gandolfi; D. Falchieri; S. Antinori. - In: NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. - ISSN 0168-9002. - STAMPA. - 530:(2004), pp. 92-97. [10.1016/j.nima.2004.05.054]
Design, Realization and Test of a Rad-Hard 2D-compressor and Packing Chip for High Energy Physics Experiments
GABRIELLI, ALESSANDRO;GANDOLFI, ENZO;FALCHIERI, DAVIDE;ANTINORI, SAMUELE
2004
Abstract
CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 mm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
