There has been a growing interest in defining models of automata enriched with time. For instance, timed automata were introduced as automata extended with clocks. In this paper, we study models of timed finite state machines (TFSMs), i.e., FSMs enriched with time, which accept timed input words and generate timed output words. Here we discuss some models of TFSMs with a single clock: TFSMs with timed guards, TFSMs with timeouts, and TFSMs with both timed guards and timeouts. We solve the problem of equivalence checking for all three models, and we compare their expressive power, characterizing subclasses of TFSMs with timed guards and of TFSMs with timeouts that are equivalent to each other.

Deterministic Timed Finite State Machines: Equivalence Checking and Expressive Power / D. Bresolin; K. El-Fakih; T. Villa; N.Yevtushenko. - In: ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE. - ISSN 2075-2180. - ELETTRONICO. - 161:(2014), pp. 203-216. (Intervento presentato al convegno GandALF 2014, Fifth International Symposium on Games, Automata, Logics and Formal Verification tenutosi a Verona nel September 10-12, 2014) [10.4204/EPTCS.161.18].

Deterministic Timed Finite State Machines: Equivalence Checking and Expressive Power

BRESOLIN, DAVIDE;
2014

Abstract

There has been a growing interest in defining models of automata enriched with time. For instance, timed automata were introduced as automata extended with clocks. In this paper, we study models of timed finite state machines (TFSMs), i.e., FSMs enriched with time, which accept timed input words and generate timed output words. Here we discuss some models of TFSMs with a single clock: TFSMs with timed guards, TFSMs with timeouts, and TFSMs with both timed guards and timeouts. We solve the problem of equivalence checking for all three models, and we compare their expressive power, characterizing subclasses of TFSMs with timed guards and of TFSMs with timeouts that are equivalent to each other.
2014
GandALF 2014, Fifth International Symposium on Games, Automata, Logics and Formal Verification
203
216
Deterministic Timed Finite State Machines: Equivalence Checking and Expressive Power / D. Bresolin; K. El-Fakih; T. Villa; N.Yevtushenko. - In: ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE. - ISSN 2075-2180. - ELETTRONICO. - 161:(2014), pp. 203-216. (Intervento presentato al convegno GandALF 2014, Fifth International Symposium on Games, Automata, Logics and Formal Verification tenutosi a Verona nel September 10-12, 2014) [10.4204/EPTCS.161.18].
D. Bresolin; K. El-Fakih; T. Villa; N.Yevtushenko
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/375465
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