Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.

Design-Space Exploration of an eFPGA Soft-Core based on Multi-Stages Switching Networks / Matteo Cuppini; Eleonora Franchi Scarselli; Claudio Mucci. - STAMPA. - (2013), pp. 133-136. (Intervento presentato al convegno Conference on Ph.D Research in Microelectronics and Electronics tenutosi a Villach, Austria nel 24-27 June 2013) [10.1109/PRIME.2013.6603104].

Design-Space Exploration of an eFPGA Soft-Core based on Multi-Stages Switching Networks

CUPPINI, MATTEO;FRANCHI SCARSELLI, ELEONORA;MUCCI, CLAUDIO
2013

Abstract

Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.
2013
Proceedings of 9th Conference on Ph.D Research on Microelectronics and Electronics
133
136
Design-Space Exploration of an eFPGA Soft-Core based on Multi-Stages Switching Networks / Matteo Cuppini; Eleonora Franchi Scarselli; Claudio Mucci. - STAMPA. - (2013), pp. 133-136. (Intervento presentato al convegno Conference on Ph.D Research in Microelectronics and Electronics tenutosi a Villach, Austria nel 24-27 June 2013) [10.1109/PRIME.2013.6603104].
Matteo Cuppini; Eleonora Franchi Scarselli; Claudio Mucci
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/192529
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