FPGA design and performance evaluation of a pulse-based echo canceler for DVB-T/H

The main design issues and performance characterization of an echo canceller for digital on-channel repeaters (OCRs) applicable to multiple standards for communications and broadcasting are addressed. In particular, in this paper we focus on a DVB-T/H scenario. The low-complexity channel cancellation technique here described is based on the introduction of a negative feedback loop capable to counterbalance the coupling effects between the OCR antennas (echoes). In the initial phase, locally generated pulse trains are transmitted to estimate the coupling channel between the transmitting and the receiving antennas. This first echo estimation is used to set-up the canceling unit, whose purpose is to generate a properly filtered replica of the repeated DVB-T/H signal compensating the echoes. After the initial set-up of the system, efficient tracking of the echoes can be performed through conventional least mean square (LMS) techniques. After developing a proper theoretical model, we introduce and discuss some important performance figures such as mean rejection ratio (MRR) and echo suppression at nominal position (ESNP). Then, a detailed description of our implementation of the echo canceller on a field programmable gate array (FPGA) board is reported. Finally, the performance of our prototype is evaluated and the measurement results are compared with those derived by the analytical model.