The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.
G. Balbi, M. Bindi, D. Falchieri, M. Furini, A. Gabrielli, A. Kugel, et al. (2013). Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card. JOURNAL OF INSTRUMENTATION, 8, 1-10 [10.1088/1748-0221/8/01/C01012].
Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
FALCHIERI, DAVIDE;GABRIELLI, ALESSANDRO;
2013
Abstract
The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
