Architecture of a slow-control ASIC for future high-energy physics experiments at S-LHC

This work is aimed at defining the architecture of a new digital ASIC, namely slow control logic (SCL), which will be designed and fabricated in a commercial 130 nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics proposed for future high-energy physics experiments at the super-Large Hadron Collider (SLHC), CERN, Geneva. The GBT link provides a transparent transport layer between the SCL and control electronics in the counting room. It will be provided with rad-hard redundant logic for critical circuits. The project follows a set of designs that were recently developed via a 250 nm CMOS technology for LHC experiments. Since this 250 nm specific technology used to design ASICs for the LHC will no longer be available as it was in the past, requesting an update technology for future experiments must be satisfied in any case. A test chip that implements three different redundant methodologies against single event effects is also described.